Paper 2014/639

Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines

Mehrdad Majzoobi, Akshat Kharaya, Farinaz Koushanfar, and Srinivas Devadas

Abstract

This paper proposes a novel approach for automated implementation of an arbiter-based physical unclonable function (PUF) on field programmable gate arrays (FPGAs). We introduce a high resolution programmable delay logic (PDL) that is implemented by harnessing the FPGA lookup-table (LUT) internal structure. PDL allows automatic fine tuning of delays that can mitigate the timing skews caused by asymmetries in interconnect routing and systematic variations. To thwart the arbiter metastability problem, we present and analyze methods for majority voting of responses. A method to classify and group challenges into different robustness sets is introduced that enhances the corresponding responses’ stability in the face of operational variations. The trade-off between response stability and response entropy (uniqueness) is investigated through comprehensive measurements. We exploit the correlation between the impact of temperature and power supply on responses and perform less costly power measurements to predict the temperature impact on PUF. The measurements are performed on 12 identical Virtex 5 FPGAs across 9 different accurately controlled operating temperature and voltage supply points. A database of challenge response pairs (CRPs) are collected and made openly available for the research community.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Keywords
PUFphysical unclonable functionFPGAhardware security
Contact author(s)
farinaz @ rice edu
History
2014-08-21: received
Short URL
https://ia.cr/2014/639
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2014/639,
      author = {Mehrdad Majzoobi and Akshat Kharaya and Farinaz Koushanfar and Srinivas Devadas},
      title = {Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines},
      howpublished = {Cryptology ePrint Archive, Paper 2014/639},
      year = {2014},
      note = {\url{https://eprint.iacr.org/2014/639}},
      url = {https://eprint.iacr.org/2014/639}
}
Note: In order to protect the privacy of readers, eprint.iacr.org does not use cookies or embedded third party content.